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Hardware and Software Design • Manufacturing Services

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PMC4U_IRUPT/PMC4U_IRUPT_CLR

[0XE0] PMC-4U Interrupt Latch read status/write clear

INTERRUPT STATUS

DATA BIT DESCRIPTION

4 SCC interrupt

3 UART D interrupt

2 UART C interrupt

1 UART B interrupt

0 UART A interrupt

FIGURE 9 PMC-4U INTERRUPT STATUS/CLEAR

The bits in this register indicate that an interrupt has been received from

the corresponding device. These bits are latched and once set will remain

set until a one is written to the bit to be cleared.

1 2 ... 16 17 18 19 20 21 22 23 24 25 26 ... 32 33

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Dynamic Engineering PMC-4U-CACI Bedienungsanleitung Seite 21